KSZ8081RNA - 10BASE-T/100BASE-TX PHY

Microchip

Datasheet Details

Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver.
RMII v1.2 Interface Support with a 50 MHz Reference Clock Output to MAC, and an Option to Input a 50 MHz Reference Clock.
RMII Back-to-Back Mode Support for a 100 Mbps Copper Repeater.
MDC/MDIO Management Interface for PHY Register Configuration.
Programmable Interrupt Output.
LED Outputs for Link and Activity Status Indication.
On-Chip Termination Resistors.

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Published: Jan 30, 2017 |