KSZ8851SNLI
Overview
- Integrated MAC and PHY Ethernet Controller Fully Compliant with IEEE 802.3/802.3u Standards
- SPI with Clock Speeds up to 40 MHz for High Throughput Applications
- Supports 10BASE-T/100BASE-TX
- Supports IEEE 802.3x Full-Duplex Flow Control and Half-Duplex Backpressure Collision Flow Control
- Supports RXQ and TXQ FIFO DMA for Fast Data Read and Write Transfers
- Supports IP Header (IPv4)/TCP/UDP/ICMP Checksum Generation and Checking
- Supports IPv6 TCP/UDP/ICMP Checksum Generation and Checking
- Automatic 32-bit CRC Generation and Checking
- Supports Simple Command and Data Phases in SPI Cycle for RXQ/TXQ FIFO and Registers Read/Write
- Supports Multiple Data Frames for TXQ FIFO and RXQ FIFO without Additional Command Phase
