PIC32CMLS00
Overview
- 32 KB Boot ROM System
- Power-on Reset (POR) and programmable Brown-out Detection (BOD)
- 16-channel Direct Memory Access Controller (DMAC)
- 12-channel event system for Inter-peripheral Core-independent Operation
- CRC-32 generator Low-Power and Power Management
- Active, Idle, Standby with partial or full SRAM retention and off sleep modes: - Active mode (< 40 μA/MHz for PL0, < 60 μA/MHz for PL2) - Idle mode (< 15 μA/MHz) with 1.5 μs wake-up time - Standby with Full SRAM retention (1.7 μA) with 2.7 μs wake-up time - Off mode (< 100 nA)
- Static and dynamic power gating architecture
- Sleepwalking peripherals
- Two performance levels
- Embedded Buck/LDO regulator with on-the-fly selection Security and Safety
