dsPIC33CK32MC105 Datasheet | Microchip Technology

Features - Small Pin Count Packages Ranging from 28 to 48 Pins, Including UQFN as Small as 4x4 mm - High-Current I/O Sink/Source - Edge or Level Change Notification Interrupt on I/O Pins - Peripheral Pin Select (PPS) Remappable Pins - Up to 64 Kbytes Flash Memory: - 10,000 erase/write cycle endurance - 20 years minimum data retention - Self-programmable under software control - Programmable code protection - Error Code Correction (ECC) - Flash OTP by ICSP™ Write Inhibit - Eight Kbytes SRAM Memory: - SRAM Memory Built-In Self-Test (MBIST) - Multiple Interrupt Vectors with Individually Programmable Priority - Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Reserved Interrupt Handling - Four External Interrupt Pins - Watchdog Timer (WDT) - Windowed Deadman Timer (DMT) - Fail-Safe Clock Monitor (FSCM) with Dedicated Oscillator - Selectable Oscillator Options Including: - High-precision, 8 MHz internal Fast RC (FRC) Oscillator - Primary high-speed, crystal/resonator oscillator or external clock - Primary PLL, which can be clocked from FRC or crystal oscillator - Low-Power Management modes (Sleep and Idle) - Power-on Reset and Brown-out Reset - On-Board Capacitorless Regulator - 256 Bytes of One-Time-Programmable (OTP) Memory  2019-2020 Microchip Technology Inc. DS70005399C-page 1 ds PIC33CK64MC105 FAMILY Peripheral Features - Two Four-Wire SPI modules (up to 50 Mbps): - 16-byte FIFO - Variable width - I2S mode - One I2C Master and Slave w/Address Masking and IPMI Support - Three Protocol UARTs with Automated Handling Support...