dsPIC33FJ64MC510A Overview
16-bit dsPIC33F CPU Code-efficient (C and Assembly) architecture Two 40-bit wide accumulators Single-cycle (MAC/MPY) with dual data fetch Single-cycle mixed-sign MUL plus hardware divide Clock Management ±2% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer (WDT) Fast wake-up and start-up Power Management Low-power management modes (Sleep,...
dsPIC33FJ64MC510A Key Features
- Two ADC modules
- Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H
- 18 analog inputs on 64-pin devices and up to 32 analog inputs on 100-pin devices
- Flexible and independent ADC trigger sources
- Up to nine 16-bit timers/counters. Can pair up to make four 32-bit timers
- Eight Output pare modules configurable as timers/counters
- Eight Input Capture modules
- Two UART modules (10 Mbps)
- With support for LIN 2.0 protocols and IrDA®
- Two 4-wire SPI modules (15 Mbps)
