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dsPIC33FJXXXMCX06A/X08A/X10A
16-bit Digital Signal Controllers (up to 256 KB Flash and 30 KB SRAM) with Motor Control and Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
Core: 16-bit dsPIC33F CPU
• Code-efficient (C and Assembly) architecture • Two 40-bit wide accumulators • Single-cycle (MAC/MPY) with dual data fetch • Single-cycle mixed-sign MUL plus hardware
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Clock Management
• ±2% internal oscillator • Programmable PLLs and oscillator clock sources • Fail-Safe Clock Monitor (FSCM) • Independent Watchdog Timer (WDT) • Fast wake-up and start-up
Power Management
• Low-power management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset • 1.
dsPIC33FJ64MC510A Datasheet
