900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Micron

MT4LC1M16C3 Datasheet Preview

MT4LC1M16C3 Datasheet

1 MEG x 16 FPM DRAM

No Preview Available !

FPM DRAM
1 MEG x 16
FPM DRAM
MT4C1M16C3, MT4LC1M16C3
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance, low-power CMOS silicon-gate
process
• Single power supply (+3.3V ±0.3V or 5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Optional self refresh (S) for low-power data
retention
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• FAST-PAGE-MODE (FPM) access
OPTIONS
• Voltage1
3.3V
5V
MARKING
LC
C
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh (16ms period)
Self Refresh (128ms period)
• Operating Temperature Range
Commercial (0oC to +70oC)
Extended (-20oC to +80oC)
DJ
TG
-5
-6
None
S2
None
ET3
Part Number Example:
MT4LC1M16C3DJ-5
NOTE: 1. The third field distinguishes the low voltage offering:
LC designates VCC = 3.3V and C designates VCC = 5V.
2. Contact factory for availability.
3. Available only on MT4C1M16C3 (5V)
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
84ns
110ns
tRAC
50ns
60ns
tPC
20ns
35ns
tAA
25ns
30ns
tCAC
15ns
15ns
tRP
30ns
40ns
PIN ASSIGNMENT (Top View)
42-Pin SOJ
44/50-Pin TSOP
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 VSS
41 DQ15
40 DQ14
39 DQ13
38 DQ12
37 VSS
36 DQ11
35 DQ10
34 DQ9
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
33 DQ8
32 NC
NC
31 CASL#
NC
30
CASH#
WE#
RAS#
29 OE#
NC
28 A9
27 A8
NC
A0
A1
26 A7
A2
25 A6
24 A5
A3
VCC
23 A4
22 VSS
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
NOTE: The # symbol indicates signal is active LOW.
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
1 MEG x 16 FPM DRAM PART NUMBERS
PART NUMBER
MT4LC1M16C3DJ-6
MT4LC1M16C3DJ-6 S
MT4LC1M16C3TG-6
MT4LC1M16C3TG-6 S
MT4C1M16C3DJ-6
MT4C1M16C3TG-6
SUPPLY PACKAGE REFRESH
3.3V
SOJ Standard
3.3V SOJ Self
3.3V
TSOP Standard
3.3V
TSOP
Self
5V SOJ Standard
5V TSOP Standard
GENERAL DESCRIPTION
The 1 Meg x 16 DRAM is a randomly accessed, solid-
state memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#). These function identi-
cally to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
Free Datasheet http://www.nDatasheet.com




Micron

MT4LC1M16C3 Datasheet Preview

MT4LC1M16C3 Datasheet

1 MEG x 16 FPM DRAM

No Preview Available !

GENERAL DESCRIPTION (continued)
the last CAS# to transition back HIGH. Use of only one
of the two results in a BYTE access cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW se-
lects an access cycle for the upper byte (DQ8-DQ15).
Each bit is uniquely addressed through the 20 ad-
dress bits during READ or WRITE cycles. These are
entered ten bits (A0-A9) at a time. RAS# is used to latch
the first ten bits and CAS# the latter ten bits. The CAS#
function is determined by the first CAS# (CASL# or
CASH#) to transition LOW and the last one to transition
back HIGH. The CAS# function also determines
whether the cycle will be a refresh cycle (RAS#-ONLY)
or an active cycle (READ, WRITE, or READ-WRITE) once
RAS# goes LOW.
The CASL# and CASH# inputs internally generate a
CAS# signal that functions identically to a single CAS#
input on other DRAMs. The key difference is that each
CAS# input (CASL# and CASH#) controls its corre-
1 MEG x 16
FPM DRAM
sponding DQ tristate logic (in conjunction with OE#
and WE#). CASL# controls DQ0-DQ7 and CASH# con-
trols DQ8-DQ15. The two CAS# controls give the
1 Meg x 16 DRAM BYTE WRITE cycle capabilities.
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE#
or CAS, whichever occurs last. Taking WE# LOW will
initiate a WRITE cycle, selecting DQ0-DQ15. If WE#
goes LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle. If WE#
goes LOW after CAS# goes LOW and data reaches the
output pins, data-out (Q) is activated and retains the
selected cell data as long as CAS# and OE# remain LOW
(regardless of WE# or RAS#). This late WE# pulse re-
sults in a READ-WRITE cycle.
The 16 data inputs and 16 data outputs are routed
through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.
FUNCTIONAL BLOCK DIAGRAM
WE#
CASL#
CASH#
CAS#
NO. 2 CLOCK
GENERATOR
COLUMN-
10 ADDRESS
BUFFER
A0
A1 REFRESH
A2 CONTROLLER
A3
A4 REFRESH
A5 COUNTER
A6
A7 10
A8
A9 ROW-
10 ADDRESS
BUFFERS (10)
RAS#
NO. 1 CLOCK
GENERATOR
1 Meg x 16 FPM DRAM
D51_5V_B.p65 Rev. B; Pub 3/01
DATA-IN BUFFER
10 COLUMN
DECODER
1,024
16
SENSE AMPLIFIERS
I/O GATING
1,024 x 16
DATA-OUT
BUFFER
16
DQ0
16
DQ15
OE#
1,024 x 1,024 x 16
10
1,024
MEMORY
ARRAY
VDD
VSS
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
Free Datasheet http://www.nDatasheet.com


Part Number MT4LC1M16C3
Description 1 MEG x 16 FPM DRAM
Maker Micron
Total Page 22 Pages
PDF Download

MT4LC1M16C3 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 MT4LC1M16C3 1 MEG x 16 FPM DRAM
Micron





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy