| Description | BALL / PIN NUMBERS FBGA TSOP G2, G3 45, 46 SYMBOL CK, CK# TYPE Input DESCRIPTION Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, i... |
| Features |
• 167 MHz Clock, 333 Mb/s/p data rate • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Co... |
| Datasheet |
 46V16M16 Datasheet - 186.82KB |
