MT47H1G4
Key Features
- Uses 2Gb Micron die
- Two ranks (includes dual CS#, ODT, and CKE balls)
- Each rank has 8 internal banks for concurrent operation
- VDD = V DDQ = +1.8V ±0.1V
- JEDEC-standard 63-ball FBGA
- Low-profile package - 1.35mm MAX thickness Functionality The 4Gb (TwinDie™) DDR2 SDRAM uses Micron’s 2Gb DDR2 monolithic die and has similar functionality. This TwinDie data sheet is intended to provide a general description, package dimensions, and the ballout only. Refer to Micron's 2Gb DDR2 data sheet for complete information or for specifications not included in this document. Options
- Configuration - 64 Meg x 4 x 8 banks x 2 ranks - 32 Meg x 8 x 8 banks x 2 ranks
- FBGA package (Pb-free) - 63-ball FBGA (9mm x 11.5mm) Rev. C
- Timing - cycle time1 - 2.5ns @ CL = 5 (DDR2-800) - 2.5ns @ CL = 6 (DDR2-800) - 3.0ns @ CL = 5 (DDR2-667) - 3.75ns @ CL = 4 (DDR2-533)
- Self refresh - Standard
