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MT4C4M4B1 - DRAM

This page provides the datasheet information for the MT4C4M4B1, a member of the MT4LC4M4B1 DRAM family.

Description

The 4 Meg x 4 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x4 configuration.

RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K).

Features

  • Industry-standard x4 pinout, timing, functions, and packages.
  • High-performance, low-power CMOS silicon-gate process.
  • Single power supply (+3.3V ±0.3V or +5V ±0.5V).
  • All inputs, outputs and clocks are TTL-compatible.
  • Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR).
  • Optional self refresh (S) for low-power data retention.
  • 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh).
  • FAST-PAGE.

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Full PDF Text Transcription

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4 MEG x 4 FPM DRAM DRAM FEATURES • Industry-standard x4 pinout, timing, functions, and packages • High-performance, low-power CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or +5V ±0.5V) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR) • Optional self refresh (S) for low-power data retention • 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) • FAST-PAGE-MODE (FPM) access • 5V tolerant inputs and I/Os on 3.3V devices MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.
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