MT4LC4M16N3 Datasheet PDF (DRAM) | Download Micron Technology MT4LC4M16N3

MT4LC4M16N3 - DRAM

This page provides the datasheet information for the MT4LC4M16N3, a member of the MT4LC4M16R6 DRAM family.

Description

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V.

The device is functionally organized as 4,194,304 locations containing 16 bits each.

Features

Single +3.3V ±0.3V power supply.
Industry-standard x16 pinout, timing, functions, and package.
12 row, 10 column addresses (R6) 13 row, 9 column addresses (N3).
High-performance CMOS silicon-gate process.
All inputs, outputs and clocks are LVTTL-compatible.
Extended Data-Out (EDO) PAGE MODE access.
4,096-cycle CAS#-BEFORE-RAS# (CBR).

Datasheet Details

Part number	MT4LC4M16N3
Manufacturer	Micron Technology
File Size	474.53 KB
Description	DRAM
Datasheet	MT4LC4M16N3 Datasheet
Additional preview pages of the MT4LC4M16N3 datasheet.

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Full PDF Text Transcription

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4 MEG x 16 EDO DRAM DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x16 pinout, timing, functions, and package • 12 row, 10 column addresses (R6) 13 row, 9 column addresses (N3) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention MT4LC4M16R6, MT4LC4M16N3 For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/dramds.

Published: Jan 16, 2006 |