MT4LC4M4E8 Datasheet PDF (4 MEG x 4 EDO DRAM) | Download Micron Technology MT4LC4M4E8

MT4LC4M4E8 - 4 MEG x 4 EDO DRAM

This page provides the datasheet information for the MT4LC4M4E8, a member of the MT4LC4M4E9 4 MEG x 4 EDO DRAM family.

Description

The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration.

RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K).

Features

Industry-standard x4 pinout, timing, functions and packages.
State-of-the-art, high-performance, low-power CMOS silicon-gate process.
Single power supply (+3.3V ±0.3V or +5V ±10%).
All inputs, outputs and clocks are TTL-compatible.
Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR).
Optional Self Refresh (S) for low-power data retention.
11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh).

Datasheet Details

Part number	MT4LC4M4E8
Manufacturer	Micron Technology
File Size	291.14 KB
Description	4 MEG x 4 EDO DRAM
Datasheet	MT4LC4M4E8 Datasheet
Additional preview pages of the MT4LC4M4E8 datasheet.

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Full PDF Text Transcription

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TECHNOLOGY, INC. 4 MEG x 4 EDO DRAM MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9 DRAM FEATURES • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art, high-performance, low-power CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or +5V ±10%) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR) • Optional Self Refresh (S) for low-power data retention • 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) • Extended Data-Out (EDO) PAGE MODE access cycle • 5V-tolerant inputs and I/Os on 3.

Published: Jan 16, 2006 |