network synchronization clock translator.
* Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL)
* Programmable DPLL/Numerically Controlled Oscillators (N.
* SyncE/SONET/SDH Timing Cards
* Synchronous Ethernet, 10 GBASE-R and 10
GBASE-W
* SONET/SDH, Fibre Channel,.
All device inputs and outputs are LVCMOS unless it is specifically stated to be differential. For the I/O column, there are digital inputs (I), digital outputs (O), analog inputs (A-I) and analog outputs (A-O).
Ball #
Name
Input Reference
M3
ref.
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