ZL30163 Overview
ZL30163 Network Synchronization Clock Translator Short Form Data Sheet.
ZL30163 Key Features
- Fully pliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL)
- Two programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronize to any clock rate from 1 Hz to 750 MHz
- Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps RMS
- Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
- DPLLs filter jitter from 0.1 mHz up to 1 kHz
- Automatic hitless reference switching and digital holdover on reference fail
- Nine input references configurable as single ended or differential and two single ended input references
- Any input reference can be fed with sync (frame pulse) or clock
- Programmable DPLLs can synchronize to sync pulse and sync pulse/clock pair
- Eight LVPECL outputs and eight LVCMOS outputs