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ZL30163 - Network Synchronization Clock Translator

General Description

All device inputs and outputs are LVCMOS unless it is specifically stated to be differential.

For the I/O column, there are digital inputs (I), digital outputs (O), analog inputs (A-I) and analog outputs (A-O).

Key Features

  • Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL).
  • Two programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronize to any clock rate from 1 Hz to 750 MHz.
  • Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps RMS.
  • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates.
  • DPLLs filter.

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📁 Similar Datasheet

Part Number Description Manufacturer
ZL30100 T1/E1 System Synchronizer Zarlink Semiconductor Inc
ZL30101 T1/E1 Stratum 3 System Synchronizer Zarlink Semiconductor Inc
ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer Zarlink Semiconductor
ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer Zarlink Semiconductor
ZL30106 SONET/SDH/PDH Network Interface DPLL Zarlink

Other Datasheets by Microsemi (now Microchip Technology)

Part Number Description
ZL30160 Four Channel Universal Clock Translator
ZL30161 Network Synchronization Clock Translator
ZL30165 Quad Clock Translator
ZL30166 Triple Channel Network Synchronization Clock Translator
ZL30167 Dual Clock Translator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ZL30163 Network Synchronization Clock Translator Short Form Data Sheet Features • Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL) • Two programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronize to any clock rate from 1 Hz to 750 MHz • Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps RMS • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates • DPLLs filter jitter from 0.