ZL30163 - Network Synchronization Clock Translator

Product Overview

Microsemi

Datasheet Details

Part number	ZL30163
Manufacturer	Microsemi
File Size	872.60 KB
Description	Network Synchronization Clock Translator
Datasheet	ZL30163 Datasheet
Additional preview pages of the ZL30163 datasheet.

Product details

Description

2 Microsemi Corporation ZL30163 Short Form Data Sheet 2.0 Pin Description All device inputs and outputs are LVCMOS unless it is specifically stated to be differential.For the I/O column, there are digital inputs (I), digital outputs (O), analog inputs (A-I) and analog outputs (A-O).Ball # Name Input Reference M3 ref0_p M4 ref0_n L3 ref1_p L4 ref1_n M5 ref2_p M6 ref2_n L5 ref3_p L6 ref3_n M7 ref4_p M8 ref4_n L7 ref5_p L8 ref5_n M9 ref6_p L9 ref6_n M10 ref7_p

Features

Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL).
Two programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronize to any clock rate from 1 Hz to 750 MHz.
Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps RMS.
Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates.
DPLLs filter.

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Other Datasheets by Microsemi

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Published: Jan 21, 2024 |