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ZL30167 - Dual Clock Translator

General Description

17 Precise Frequency Monitor (PFM) 18 Guard Soak Timer (GST) 31 Figure 14 "Typical Power-Up Reset and Configuration Circuit" 32 5.1, “ZL30167 Configuration programming“ 93 Register Name: phasemem_limit_ref0 130 Register Name: dpll0_df_offset 173 13.0, “Package Markings“ Change Included

Key Features

  • Two independent clock channels.
  • Two programmable digital PLLs/Numerically Controlled Oscillators (NCOs).
  • Four precision synthesizers generate any clockrate from 1 Hz to 750 MHz with low jitter for 10 G PHYs.
  • Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz.
  • Automatic hitless reference switching and digital holdover on reference fail.
  • Nine input references configurable as single ended or differential and two singl.

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ZL30167 Dual Clock Translator Data Sheet Features • Two independent clock channels • Two programmable digital PLLs/Numerically Controlled Oscillators (NCOs) • Four precision synthesizers generate any clockrate from 1 Hz to 750 MHz with low jitter for 10 G PHYs • Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz • Automatic hitless reference switching and digital holdover on reference fail • Nine input references configurable as single ended or differential and two single ended input references • Phase alignment to input 1 Hz frame pulse with associated reference clock (ref/sync pairing) • Any input reference can be fed with sync (frame pulse) or clock • Digital PLLs filter jitter at 5.