ZL30773 Datasheet | Microsemi

Features - One, Two or Three DPLL Channels - Packet and/or physical-layer frequency, phase and time synchronization - Physical-layer pliance with ITU-T G.8262, G.8261.1, G.813, G.812, Telcordia GR-1244, GR-253 - Packet-timing pliance with ITU-T G.8261, G.8263, G.8273.2 (class A, B, C, D), G.8273.4 - Enables 5G wireless applications with sub100ns time/phase alignment requirements - Programmable bandwidth, 0.1m Hz to 470Hz - Hitless reference switching and mode switching - High-resolution holdover averaging - Programmable phase slope limit for transients, downto 1 ns/s - Per-DPLL phase adjustment, 1ps resolution - Input Clocks - Accepts up to 10 differential or CMOS inputs - Any input frequency from 0.5Hz to 900MHz - Per-input activity and frequency monitoring - Automatic or manual reference switching - Fast lock to 1 PPS input, <30 seconds - Any input can be a 1PPS SYNC input for REF+SYNC frequency/phase/time locking - Per-input phase adjustment, 1ps resolution - Output Clock Frequency Generation - Any output frequency from <0.5Hz to 1045MHz (180MHz max for Synth0) - High-resolution fractional frequency conversion with 0ppm error - Synthesizers 1 & 2 have integer and fractional dividers to make a total of 5 frequency families - Output jitter from Synths 1 & 2 is <0.3ps RMS - Output jitter from fractional dividers is typically < 1ps RMS, many frequencies <0.5ps RMS - Each HPOUTP/N pair can be LVDS, LVPECL, HCSL, 2x CMOS, HSTL or programable diff. - Four output banks each with VDDO pin; CMOS output voltages from 1.5V to 3.3V - Per-synthesizer phase adjust, 1ps resolution ZL30771, ZL30772, ZL30773 IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers Product Brief November 2019 Ordering Information ZL30771LFG7 1-Channel 80-lead LGA Trays ZL30772LFG7 2-Channel 80-lead LGA Trays ZL30773LFG7 3-Channel 80-lead LGA Trays Ni Au (Pb-free) Package size: 11 x 11 mm -40C to +85C - Per-output programmable duty cycle - Precise output alignment circuitry and peroutput...