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  Microsemi Electronic Components Datasheet  

ZL40293 Datasheet

20-Output PCIe Gen Buffer

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Data Sheet
ZL40293
20-Output PCIe Gen 1, 2 ,3, 4 and 5 Buffer with Ultra-Low
Additive Jitter
Features
Fully Compliant with PCIe 1, 2, 3, 4 and 5
Specifications
Ordering Information
ZL40293LDG1
ZL40293LDF1
72 pin QFN Trays
72 pin QFN Tape and Reel
20 Low-Power Push-Pull HCSL PCIe Outputs
Ultra-low additive jitter: 10fs maximum
Package size: 10 x 10 mm
-40C to +85C
Supports clock frequencies from 0 to 250MHz
Applications
Supports 3.3V power supplies
Embedded Low Drop Out (LDO) Voltage regulator
provides superior Power Supply Noise Rejection
PCI Express generation 1/2/3/4/5 clock distribution
Intel QPI
Servers
Maximum output to output skew of 50ps
Storage and Data Centers
SMBus Interface
Switches and Routers
Eight OE pins
Embedded series terminations adjusted for 100
differential transmission line
Transparent for Spread-Spectrum Clock
VDD VDD_A
CLK_IN
CLK_IN#
SA_0
SA_1
SDA
SCL
PWRGD/PWRDN#
OE#[12:5]
RFU
CK[19:0]
Control
Logic
R_COMP
GND GND_A
March 2019
© 2019 Microsemi Corporation
Figure 1. Functional Block Diagram
ZL40293
1


  Microsemi Electronic Components Datasheet  

ZL40293 Datasheet

20-Output PCIe Gen Buffer

No Preview Available !

Table of Contents
Data Sheet
ZL40293
Features..................................................................................................................................... 1
Applications................................................................................................................................ 1
Table of Contents ...................................................................................................................... 2
Pin Diagram ............................................................................................................................... 5
Pin Descriptions ......................................................................................................................... 6
Functional Description ............................................................................................................... 8
Clock Inputs ............................................................................................................................... 8
Clock Outputs ............................................................................................................................ 9
Termination of unused outputs ................................................................................................ 10
Power Supply Filtering............................................................................................................. 10
OE# and Output Enables (Control Register) ........................................................................... 10
OE# Assertion (Transition from ‘1’ to ‘0’) ................................................................................. 10
OE# De-Assertion (Transition from ‘0’ to ‘1’) ........................................................................... 11
PWRGD / PWRDN# ................................................................................................................ 11
PWRDN# Assertion ................................................................................................................. 11
PWRGD Assertion ................................................................................................................... 11
Programming via SMBus ......................................................................................................... 13
SMBus Byte Read/Write .......................................................................................................... 13
SMBus Block Read/Write ........................................................................................................ 14
Register Map ........................................................................................................................... 16
AC and DC Electrical Characteristics ...................................................................................... 19
Absolute Maximum Ratings ..................................................................................................... 19
Current Consumption............................................................................................................... 19
DC Electrical Specification....................................................................................................... 20
Power Noise Tolerance ........................................................................................................... 20
PCIe Electrical Characteristics ................................................................................................ 21
Input Clock Requirements ....................................................................................................... 25
SMBus Electrical Characteristics............................................................................................. 26
Package Outline ...................................................................................................................... 28
March 2019
© 2019 Microsemi Corporation
ZL40293
2


Part Number ZL40293
Description 20-Output PCIe Gen Buffer
Maker Microsemi
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ZL40293 Datasheet PDF






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