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ZL40293 - 20-Output PCIe Gen Buffer

General Description

6 Functional Description 8 Clock Inputs 8 Clock Outputs 9 Termination of unused outputs 10 Power Supply Filtering 10 OE# and Output Enables (Control Register) 10 OE# Assertion (Transition from ‘1’ to ‘0’) 10 OE# De-Assertion (Transition from ‘0’ to ‘1’) 11 PWRGD / PWRDN# 11 PWRDN# Assertio

Key Features

  • Fully Compliant with PCIe 1, 2, 3, 4 and 5 Specifications Ordering Information ZL40293LDG1 ZL40293LDF1 72 pin QFN Trays 72 pin QFN Tape and Reel.
  • 20 Low-Power Push-Pull HCSL PCIe Outputs.
  • Ultra-low additive jitter: 10fs maximum Package size: 10 x 10 mm -40C to +85C.
  • Supports clock frequencies from 0 to 250MHz.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Data Sheet ZL40293 20-Output PCIe Gen 1, 2 ,3, 4 and 5 Buffer with Ultra-Low Additive Jitter Features • Fully Compliant with PCIe 1, 2, 3, 4 and 5 Specifications Ordering Information ZL40293LDG1 ZL40293LDF1 72 pin QFN Trays 72 pin QFN Tape and Reel • 20 Low-Power Push-Pull HCSL PCIe Outputs • Ultra-low additive jitter: 10fs maximum Package size: 10 x 10 mm -40C to +85C • Supports clock frequencies from 0 to 250MHz Applications • Supports 3.