PDSP16256GC1R Overview
The PDSP16256 contains sixteen multiplier accumulators, which can be multi cycled to provide from 16 to 128 stages of digital filtering. Input data and coefficients are both represented by 16-bit two’s plement numbers with coefficients converted internally to 12 bits and the results being accumulated up to 32 bits. In 16-tap mode the device samples data at the system clock rate of up to 25MHz.
PDSP16256GC1R Key Features
- See notes following Electrical Characteristics for further information on MIL-STD-883 screening