Datasheet4U Logo Datasheet4U.com

M2S56D20ATP Datasheet 256m Double Data Rate Synchronous Dram

Manufacturer: Mitsubishi Electric

Overview: DDR SDRAM (Rev.1.2) Jun. '01 Preliminary MITSUBISHI LSIs M2S56D20/ 30/ 40ATP 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice.

General Description

M2S56D20ATP is a 4-bank x 16,777,216-word x 4-bit, M2S56D30ATP is a 4-bank x 8,388,608-word x 8-bit, M2S56D40ATP is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK.

Key Features

  • - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmabl.

M2S56D20ATP Distributor & Price

Compare M2S56D20ATP distributor prices and check real-time stock availability from major suppliers. Prices and inventory may vary by region and order quantity.

More Datasheets from Mitsubishi Electric

Part Number Description
M2S56D20ATP-10 256M Double Data Rate Synchronous DRAM
M2S56D20ATP-10L 256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75 256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75A 256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75AL 256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75L 256M Double Data Rate Synchronous DRAM
M2S56D20ATP75A 256M Double Data Rate Synchronous DRAM
M2S56D20AKT 256M Double Data Rate Synchronous DRAM
M2S56D20AKT-10 256M Double Data Rate Synchronous DRAM
M2S56D20AKT-10L 256M Double Data Rate Synchronous DRAM