M66282FP Datasheet | Mitsubishi Electric

MITSUBISHI <DIGITAL ASSP> 8192 x 8-BIT LINE MEMORY DESCRIPTION The M66282FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 8192 words x 8 bits. The M66282FP, performing reading and writing operations at different cycles independently and asynchronously, is optimal for buffer memory to be used between equipment of different data processing speeds. PIN CONFIGURATION (TOP VIEW) Q0 DATA OUTPUT Q1 Q2 Q3 READ ENABLE REB INPUT READ RESET RRESB INPUT GND READ CLOCK INPUT RCK Q4 DATA OUTPUT 1 2 3 4 5 6 7 8 9 24 D0 23 D1 22 D2 21 D3 WRITE ENABLE INPUT WRITE RESET 19 WRESB INPUT 20 WEB 18 VCC 17 WCK 16 D4 15 D5 DATA INPUT 14 D6 13 D7 WRITE CLOCK INPUT DATA INPUT Features - - - - - Memory configuration 8192 words x 8 bits (dynamic memory) High speed cycle 25 ns (Min.) High speed access 18 ns (Max.) Output hold 3 ns (Min.) Reading and writing operations can be pletely carried out independently and asynchronously. - Variable length delay bit - Input/output TTL direct connection allowable - Output 3 states Q5 10 Q6 11 Q7 12 APPLICATION - Digital copying machine, laser beam printer, high speed facsimile, etc. Outline 24P2Q-A(SSOP) FUNCTION When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising edge of write lock input WCK to perform writing operation. When this is the case,the write address counter is also incremented simultaneously. When WEB is set to "H", the writing operation is inhibited and the write address counter stops. When write reset input WRESB is set to "L", the write address counter is initialized. When read enable input REB is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counter is incremented...