M66852FP Description
M66850/851/852/853 are very high-speed and clock synchronous FIFO(First-In,First-Out) memories fabricated by high-speed CMOS technology. These FIFOs are applicable for a data buffer as networks and munications. The write operation is controlled by a write clock pin(WCLK) and two write enable pins(WEN1,WEN2).
M66852FP Key Features
- Data Buffer for networks munications
- 853FP)
- INPUT REGISTER
- VCC One+5 volt power supply pin
- GND One 0 volt ground pin
- RS : Reset(INPUT) When RS is set LOW, internal read and write pointers are set to the first physical location,the output
- WCLK : Write Clock(INPUT) Data present on D0-D8 is written into the FIFO on the rising edge of WCLK when the FIFO is ena
- RCLK : Read Clock(INPUT) Data is read from the FIFO on the rising edge of RCLK when the FIFO is enabl