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Motorola Electronic Components Datasheet

MC100EL14 Datasheet

1:5 Clock Distribution Chip

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:5 Clock Distribution Chip
The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. The LVEL14 is
functionally and pin compatible with the EL14 but is designed to operate
in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or
3.0V to 3.8V). If a single-ended input is to be used the VBB output should
be connected to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the switching reference
for the input of the LVEL14 under single-ended input conditions, as a
result this pin can only source/sink up to 0.5mA of current.
The LVEL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by the input
pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This avoids
any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock, therefore
all associated specification limits are referenced to the negative edge of
the clock input.
50ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
75kInternal Input Pulldown Resistors
>2000V ESD Protection
VEE Range of –3.0V to –5.5V
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC EN VCC NC SCLK CLK CLK VBB SEL VEE
20 19 18 17 16 15 14 13 12 11
10
D
Q
1 2 3 4 5 6 7 8 9 10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4
MC100LVEL14
MC100EL14
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN DESCRIPTION
PIN FUNCTION
CLK
SCLK
EN
SEL
VBB
Q0–4
Diff Clock Inputs
Scan Clock Input
Sync Enable
Clock Select Input
Reference Output
Diff Clock Outputs
FUNCTION TABLE
CLK SCLK SEL EN
L X LL
H X LL
X L HL
X H HL
X X XH
* On next negative transition of
CLK or SCLK
Q
L
H
L
H
L*
7/95
© Motorola, Inc. 1996
4–1
REV 1


Motorola Electronic Components Datasheet

MC100EL14 Datasheet

1:5 Clock Distribution Chip

No Preview Available !

MC100LVEL14 MC100EL14
ABSOLUTE MAXIMUM RATINGS1
Symbol
Characteristic
Rating
Unit
VEE
VI
Iout
Power Supply (VCC = 0V)
Input Voltage (VCC = 0V)
Output Current
Continuous
Surge
–8.0 to 0
0 to –6.0
50
100
VDC
VDC
mA
TA Operating Temperature Range
–40 to +85
VEE
Operating Range1,2
–5.7 to –4.2
1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at: 100EL Series: –4.20V to –5.50V
10EL Series: –4.94V to –5.50V
°C
V
DC CHARACTERISTICS (VEE = VEE(min) – VEE(max); VCC = GND1)
–40°C
0°C to 85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Unit Condition
VOH
Output HIGH Voltage
–1085 –1005 –880 –1025 –955
–880
mV VIN = VIH(max)
VOL
Output LOW Voltage
–1830 –1695 –1555 –1810 –1705 –1620 mV or VIL(min)
VOHA Output HIGH Voltage
–1095
— –1035 —
— mV VIN = VIH(max)
VOLA
Output LOW Voltage
— — –1555 — — –1610 mV or VIL(min)
VIH Input HIGH Voltage
–1165
–880 –1165
–880
mV
VIL Input LOW Voltage
–1810 — –1475 –1810 — –1475 mV
IIL Input LOW Current
CLK –300
— –300 —
µA VIN = VIL(max)
Others 0.5
0.5
1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = –4.5V now apply across
the full VEE range of –3.0V to –5.5V. Outputs are terminated through a 50resistor to –2.0V except where otherwise specified on the individual
data sheets.
MOTOROLA
4–2 ECLinPS and ECLinPS Lite
DL140 — Rev 3


Part Number MC100EL14
Description 1:5 Clock Distribution Chip
Maker Motorola
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MC100EL14 Datasheet PDF






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