low voltage 1:15 differential ecl/pecl clock divider and fanout buffer.
15 differential ECL/PECL outputs (4 output banks) 2 selectable differential ECL/PECL inputs Selectable ÷1 or ÷2 frequency divider 130 ps maximum device skew Supports DC t.
that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differe.
The MC100ES6222 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and six differ.
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