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MC100H642 Datasheet

68030/040 PECL-TTL CLOCK DRIVER

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
68030/040 PECL-TTL Clock Driver
The MC10H/100H642 generates the necessary clocks for the 68030,
68040 and similar microprocessors. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of part–to–part
skew, within–part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced to
+5.0V) for the input clock. TTL clocks are typically used in present MPU
systems. However, as clock speeds increase to 50MHz and beyond, the
inherent superiority of ECL (particularly differential ECL) as a means of
clock signal distribution becomes increasingly evident. The H642 also
uses differential PECL internally to achieve its superior skew
characteristic.
The H642 includes divide–by–two and divide–by–four stages, both to
achieve the necessary duty cycle skew and to generate MPU clocks as
required. A typical 50MHz processor application would use an input clock
running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz
(see Logic Diagram).
The 10H version is compatible with MECL 10HECL logic levels,
while the 100H version is compatible with 100K levels (referenced to
+5.0V).
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0V Supply
MC10H642
MC100H642
68030/040
PECL–TTL CLOCK
DRIVER
26
45
11
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
Function
Reset(R): LOW on RESET forces all Q outputs LOW.
Select(SEL): LOW selects the ECL input source (DE/DE).
HIGH selects the TTL input source (DT).
The H642 also contains circuitry to force a stable input state of the ECL differential input pair, should both sides be left open. In
this Case, the DE side of the input is pulled LOW, and DE goes HIGH.
Power Up: The device is designed to have positive edges of the ÷2 and ÷4 outputs synchronized at Power Up.
VT VT Q1 GT GT Q0 VT
25 24 23 22 21 20 19
Q2 26
18 VBB
GT 27
17 DE
GT 28
Q3 1
VT 2
Pinout: 28–Lead PLCC
(Top View)
16
15
14
DE
VE
R
VT 3
13 GE
Q4 4
12 DT
5 6 7 8 9 10 11
Q5 GT GT Q6 Q7 VT SEL
9/96
© Motorola, Inc. 1996
2–1
REV 4


Motorola Electronic Components Datasheet

MC100H642 Datasheet

68030/040 PECL-TTL CLOCK DRIVER

No Preview Available !

MC10H642 MC100H642
LOGIC DIAGRAM
TTL Outputs
Q7
TTL/ECL Clock Inputs
VBB
DE
DE MUX
DT
SEL
÷4
Q6
Q5
Q4
Q3
Q2
TTL Control Inputs
R
÷2 Q1
Q0
PIN NAMES
Pin Symbol
81 Q3
82 VT
83 VT
84 Q4
85 Q5
86 GT
87 GT
88 Q6
89 Q7
10 VT
11 SEL
12 DT
13 GE
14 R
**Divide by 2
**Divide by 4
Description
Signal Output (TTL)**
TTL VCC (+5.0V)
TTL VCC (+5.0V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL Ground (0V)
TTL Ground (0V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL VCC (+5.0V)
Input Select (TTL)
TTL Signal Input
ECL Ground (0V)
Reset (TTL)
Pin Symbol Description
15 VE ECL VCC (+5.0V)
16 DE ECL Signal Input (Non–Inverting)
17 DE ECL Signal Input (Inverting)
18
VBB
VBB Reference Output
19 VT TTL VCC (+5.0V)
20 Q0 Signal Output (TTL)*
21 GT TTL Ground (0V)
22 GT TTL Ground (0V)
23 Q1 Signal Output (TTL)*
24 VT TTL VCC (+5.0V)
25 VT TTL VCC (+5.0V)
26 Q2 Signal Output (TTL)**
27 GT TTL Ground (0V)
28 GT TTL Ground (0V)
MOTOROLA
2–2 MECL Data
DL122 — Rev 6


Part Number MC100H642
Description 68030/040 PECL-TTL CLOCK DRIVER
Maker Motorola
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MC100H642 Datasheet PDF






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