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MC100LVE310 Datasheet

Low Voltage 2:8 Differential Fanout Buffer

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage 2:8 Differential
Fanout Buffer
ECL/PECL Compatible
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device features
fully differential clock paths to minimize both device and system skew.
The LVE310 offers two selectable clock inputs to allow for redundant or
test clocks to be incorporated into the system clock trees. The
MC100E310 is pin compatible to the National 100310 device. The
MC100LVE310 works from a –3.3V supply while the MC100E310
provides identical function and performance from a standard –4.5V 100E
voltage supply.
MC100LVE310
MC100E310
LOW VOLTAGE
2:8 DIFFERENTIAL
FANOUT BUFFER
Dual Differential Fanout Buffers
200ps Part–to–Part Skew
50ps Output–to–Output Skew
Low Voltage ECL/PECL Compatible
28–lead PLCC Packaging
For applications which require a single–ended input, the VBB reference
voltage is supplied. For single–ended input applications the VBB
reference should be connected to the CLK input and bypassed to ground
via a 0.01µf capacitor. The input signal is then driven into the CLK input.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50, even if only
one side is being used. In most applications all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used it is necessary to terminate at least the output pairs
adjacent to the output pair being used in order to maintain minimum skew.
Failure to follow this guideline will result in small degradations of
propagation delay (on the order of 10–20ps) of the outputs being used,
while not catastrophic to most designs this will result in an increase in
skew. Note that the package corners isolate outputs from one another
such that the guideline expressed above holds only for outputs on the
same side of the package.
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
The MC100LVE310, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the
LVE310 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE310’s
performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage
of VCC–2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note
AN1406/D.
7/95
© Motorola, Inc. 1996
4–1
REV 0.1


Motorola Electronic Components Datasheet

MC100LVE310 Datasheet

Low Voltage 2:8 Differential Fanout Buffer

No Preview Available !

MC100LVE310 MC100E310
Q0 Q0 Q1 VCCO Q1 Q2 Q2
25 24 23 22 21 20 19
VEE 26
18
CLK_SEL 27
17
Q3
Q3
CLKa 28
VCC 1
CLKa 2
16 Q4
Pinout: 28–Lead PLCC
(Top View)
15
VCCO
14 Q4
VBB
CLKb
3 13
4 12
5 6 7 8 9 10 11
CLKb NC Q7 VCCO Q7 Q6 Q6
Q5
Q5
PIN NAMES
Pins
CLKa, CLKb
Q0:7
VBB
CLK_SEL
CLK_SEL
0
1
Function
Differential Input Pairs
Differential Outputs
VBB Output
Input Clock Select
Input Clock
CLKa Selected
CLKb Selected
CLKa
CLKa
CLKb
CLKb
CLK_SEL
LOGIC SYMBOL
VBB
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
MOTOROLA
4–2 ECLinPS and ECLinPS Lite
DL140 — Rev 3


Part Number MC100LVE310
Description Low Voltage 2:8 Differential Fanout Buffer
Maker Motorola
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MC100LVE310 Datasheet PDF






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