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MC10175 - Quint Latch

Download the MC10175 datasheet PDF. This datasheet also covers the MC10175L variant, as both devices belong to the same quint latch family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • five D type latches with common reset and a common two.
  • input clock. Data is transferred on the negative edge of the clock and latched on the positive edge. The two clock inputs are “OR”ed together. Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. The reset.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MC10175L_MotorolaInc.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MC10175 Quint Latch ON Semiconductor
MC10171 Dual Binary to 1-4 Decoder(Low) ON Semiconductor
MC10173 Quad 2-Input Multiplexer/Latch ON Semiconductor
MC10174 Dual 4 to 1 Multiplexer ON Semiconductor
MC10176 Hex D Master/Slave Flip-Flop ON Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MC10170 9+2-Bit Parity Generator/Checker
MC10171 Dual Binary to 1-4 Decoder
MC10172 Dual Binary to 1-4 Decoder
MC10173 Quad 2-Input Multiplexer / Latch
MC10174 Dual 4 to 1 Multiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quint Latch The MC10175 is a high speed, low power quint latch. It features five D type latches with common reset and a common two–input clock. Data is transferred on the negative edge of the clock and latched on the positive edge. The two clock inputs are “OR”ed together. Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. The reset input is enabled only when the clock is in the high state. PD = 400 mW typ/pkg (No Load) tpd = 2.5 ns typ (Data to Output) tr, tf = 2.