MC10E1651 Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual ECL Output parator With Latch The MC10E1651 is functionally and pin-for-pin patible with the MC1651 in the MECL III family, but is fabricated using Motorola’s advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output patibility with 10KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package. The latch enable (LENa and LENb) input pins operate from standard ECL 10KH logic levels. When the latch enable is at a logic high level the MC10E1651 acts as a parator, hence Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the plement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met. - Typ. 3.0 d B Bandwidth...