MC10E451 Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6ĆBit D Register Differential Data and Clock The MC10E/100E451 contains six D-type flip-flops with single-ended outputs and differential data inputs. The mon clock input is also differential. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Master Reset (MR) input resets all Q outputs to LOW. The VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only. When using for this purpose, it is remended that VBB is decoupled to VCC via a 0.01µF capacitor. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an...