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MC10ELT21 - Differential PECL to TTL Translator

Download the MC10ELT21 datasheet PDF. This datasheet also covers the MC100ELT21 variant, as both devices belong to the same differential pecl to ttl translator family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • The VBB output allows the ELT21 to also be used in a single-ended input mode. In this mode the VBB output is tied to the IN input for a non-inverting buffer or the IN input for an inverting buffer. If used the VBB pin should be bypassed to ground via a 0.01µF capacitor. The ELT21 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels.
  • 3.5ns Typical Propagation Delay.
  • Di.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MC100ELT21-Motorola.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MC10ELT21 Differential PECL to TTL Translator ON Semiconductor
MC10ELT20 TTL to Differential PECL Translator ON Semiconductor
MC10ELT22 Dual TTL to Differential PECL Translator ON Semiconductor
MC10ELT24 TTL to Differential ECL Translator ON Semiconductor
MC10ELT25 Differential ECL to TTL Translator ON Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MC10ELT20 TTL to Differential PECL Translator
MC10ELT22 Dual TTL to Differential PECL Translator
MC10ELT24 TTL to Differential ECL Translator
MC10ELT25 Differential ECL to TTL Translator
MC10ELT26 1:2 Fanout Differential PECL to TTL Translator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential PECL to TTL Translator The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of the ELT21 makes it ideal for those applications where space, performance and low power are at a premium. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The VBB output allows the ELT21 to also be used in a single-ended input mode. In this mode the VBB output is tied to the IN input for a non-inverting buffer or the IN input for an inverting buffer. If used the VBB pin should be bypassed to ground via a 0.01µF capacitor.