MC14044B Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA CMOS MSI Quad R- S Latches The MC14043B and MC14044B quad R- S latches are constructed with MOS P- channel and N- channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three- state buffers having a mon enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs. - Double Diode Input Protection - Three- State Outputs with mon Enable - Outputs Capable of Driving Two Low- power TTL Loads or One Low- Power Schottky TTL Load Over the Rated Temperature Range - Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14043B MC14044B L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = - 55° to 125°C for all packages. MC14043B 4 S0 2 Q0 MC14044B 4 R0 13 Q0 3 R0 6 S1 9 Q1 3 S0 6 R1 9...