Datasheet4U Logo Datasheet4U.com

MC54HC132A - Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

📥 Download Datasheet

Datasheet preview – MC54HC132A

📁 Similar Datasheet

  • MC54HC4016 - Quad Analog Switch/ Multiplexer/Demultiplexer (ON Semiconductor)
  • MC5402F - Quad 2-Input NOR Gate (Motorola Semiconductor)
  • MC54F161A - Synchronous 4-Bit Decade Counter (Motorola Semiconductor)
  • MC54F163A - Synchronous 4-Bit Binary Counter (Motorola Semiconductor)
  • MC54F164 - 8-Bit Serial-In Parallel-Out Shift Register (Motorola Semiconductor)
  • MC54F168 - (MC54F168 / MC54F169) 4-Stage Synchronous Bidirectional Counters (Motorola Semiconductor)
  • MC54F169 - (MC54F168 / MC54F169) 4-Stage Synchronous Bidirectional Counters (Motorola Semiconductor)
  • MC504 - (MC504 / MC554) EXPANDABLE 3-WIDE 3-INPUT AND-OR-INVERT GATE (ETC)
  • MC509 - (MC509 / MC559) 4 wide 3-2-2-3 input expander (ETC)
  • MC50XS4200BEK - Dual 24V high-side switch (NXP)
Other Datasheets by Motorola
  • MC54HC138 - 1-of-8 Decoder / Demultiplexer High-Performance Silicon-Gate CMOS
  • MC54HC138A - 1-of-8 Decoder/Demultiplexer
  • MC54HC138A - 1-OF-8 DECODER / DEMULTIPLEXER
  • MC54HC139A - Dual 1-of-4 Decoder/Demultiplexer
  • MC54HC14 - Hex Schmitt-Trigger Inverter
  • MC54HC14A - Hex Schmitt-Trigger Inverter
  • MC54HC14A - HEX Schmitt-Trigger Inverter High-Performance Silicon-Gate CMOS
  • MC54HC154 - 1-of-16 Decoder/Demultiplexer

Full PDF Text Transcription

Click to expand full text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High–Performance Silicon–Gate CMOS The MC54/74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhance noise immunity or to square up slowly changing waveforms. • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No.
Published: |