Control Loops
The inputs to the device are 6 bit I and Q digital
signals. A pin programmable input format selector al-
lows use of A/D converters with either offset binary or
2’s complement output format. The A/D output data is
fed into the carrier synchronization loop which is capa-
ble of locking onto signals with frequency offsets as
large as the baud rate. The carrier synchronizer in-
cludes a complex multiplier, a phase detector, a pro-
grammable second order loop filter, a phase lock
detector, a false lock detector and a frequency sweep
function. The carrier tracking loop is closed digitally us-
ing an internal numerically controlled oscillator (NCO).
The frequency sweep rate, the frequency sweep limit,
the phase and frequency lock detector thresholds and
the loop parameters are programmable. The I and Q
QPSK symbols produced in this loop are further pro-
cessed by a Decimation Filter and a Half Nyquist Filter
(roll-off factor of 0.35) to perform the matched filtering.
Once processed, the filtered data samples are passed
to the data estimator which produces 3 bits of I and Q
soft decision data (device output) as well as I and Q er-
ror vectors.
The demodulator also performs a non-coherent
automatic gain control (AGC) function on the IF signal
using a total power algorithm and generates a single bit
output signal which must be lowpass filtered and inter-
faced to the gain control port of a variable gain amplifi-
er. The AGC includes a programmable second order
loop filter.
the oversampling factor. Its output signal levels must be
suitable for clocking both the A/D converter and the
QPSK demodulator.
Decimation Filter
The Decimation Filter block consists of three swit-
chable decimation filters: two 1/2-band filters and a 2/3-
band filter. Together with a switchable input decimation
of 2, the decimation filter block enables the demodula-
tor to operate at an oversampling ratio of 2, 3, 4, 6, 8,
12, or 16. The variable sampling demodulator minimiz-
es the external components to build a Set Top box for
the whole range of data rates. In order to compensate
different signal gains after the decimation an internal
Digital AGC produces a control signal which adjusts the
gain after the complex multiplier.
I2C interface
The MC92303 is a slaved device that is intended
to be controlled via the I2C interface. In accordance
with the I2C specification, the I2C master initiates all
data transfers to and from the demodulator and pro-
vides the I2C clock. Data is always transferred one byte
at a time, MSB first, and the receiver must acknowledge
each byte by pulling the data line low during the cycle
following the LSB. The demodulator interprets the byte
following its slave address as an 8-bit sub-address
which selects a particular register to be written to or
read from.
Application
Another control loop, the mid-symbol sampling
synchronization loop, ensures that the optimum A/D
sampling times are determined by providing a single bit
output signal to a voltage controlled oscillator (VCO)
clock generator. This VCO quiescent frequency is auto-
matically set to 2, 3, 4, 6, 8,12 or 16 Rs depending on
The demodulator can be used to implement a DVB
compliant demodulator with the circuitry shown in Fig-
ure 2. The 3 bit soft decision data of the demodulator is
connected directly toa Viterbi Decoder or a combined
Viterbi and Reed Solomon Decoder.
Clock
VCO
Host
CPU
I2C
from LNB
Freq. = 0 Hz
1st IF Freq.
0.95 - 2.15 GHz
2nd IF Freq.
480 MHz
0°
LO
A
D
VCO
I[5:0] SDA
I_soft[2:0]
MC92303
MC92302
VI1[2:0]
DO[7:0]
Freq.
Synthesizer
90°
Q_soft[2:0]
VI0[2:0]
A
D Q[5:0]
AGC
MOTOROLA
2
Figure 2. DVB Application Example
MC92303
Rev.1.3
