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MC92501 Datasheet

ATM Cell Processor

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
ATM Cell Processor
The ATM Cell Processor (MC92501) is an Asynchronous Transfer Mode (ATM)
layer device composed of dedicated high-performance ingress and egress cell
processors combined with UTOPIA Level 2-compliant physical (PHY) and switch
interface ports (see Block Diagram). The MC92501 is a second generation ATM
cell processor in MotorolaÕs 92500 series. This document provides information
on the new features offered by the second generation ATM cell processor. This
document, combined with MC92500/D, provides the complete speciÞcation for
the ATM cell processor.
New Features of the MC92501:
¥ Implements ATM Layer Functions for Broadband ISDN According to ATM
Forum UNI 4.0 and TM 4.0 SpeciÞcations, ITU Recommendations, and
Bellcore Recommendations
¥ Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0
¥ Selective Discard CLP = 1 (or CLP = 0+1) Flow on Selected Connections
¥ UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface
¥ Supports Both Partial Packet Discard (PPD) and Early Packet Discard (EPD)
¥ Change ABR RM Cell Priority
¥ Support for CLP Transparency
Existing MC92500 Features:
¥ Full-Duplex Operation at Data Rates up to 155 Mbit/sec
¥ Performs Internal VPI and VCI Address Compression for up to 64K VCs
¥ CLP-Aware Peak, Average, and Burst-Length Policing with Programmable
Tag/Drop Action Per Policer
¥ Supports up to 16 Physical Links Using Dedicated Ingress/Egress MultiPHY
Control Signals
¥ Each Physical Link Can Be ConÞgured as Either a UNI or NNI Port
¥ Supports Multicast, Multiport Address Translation
¥ Maintains Both Virtual Connection and Physical Link Counters on Both
Ingress and Egress Cell Flows
¥ Provides a Flexible 32-Bit External Memory Port for Context Management
¥ Automated AIS, RDI, CC, and Loopback Functions with Performance
Monitoring Block Test on All 64K Connections
¥ Programmable 32-Bit Microprocessor Interface Supporting Big-Endian or
Little-Endian Bus Formats
¥ Bidirectional UPC or NPC Design with up to Four Leaky Buckets Per
Connection
¥ Supports a Programmable Number of Additional Switch Overhead
Parameters Allowing Adaptation to Any Switch Routing Header Format
¥ Provides Per-Link Cell Counters in Both Directions
Order this document
by MC92501/D
MC92501
GC SUFFIX
GTBGA
CASE 1208
ORDERING INFORMATION
MC92501GC GTBGA
This document contains information on a new product. SpeciÞcations and information herein are subject to change without notice.
REV 1.2
2/98
TN98020500
M© MOoTtoOrolRa,OInLc.A1998
MC92501
1


Motorola Electronic Components Datasheet

MC92501 Datasheet

ATM Cell Processor

No Preview Available !

UTOPIA IF
EXTERNAL
MEMORY IF
REPRESENTATIVE BLOCK DIAGRAM
INGRESS PHY IF
CRC Check (OAM)
MultiPHY Support
INTERNAL SCAN
INGRESS CELL PROCESSOR
VP and VC Address Translation
NPC/UPC
Cell Counting
OAM Operations
Add Switch Parameters
Microprocessor Cell Insertion/Extraction
EXT MEMORY IF
FMC GENERATION
INGRESS SWITCH IF
CRC Generation
Independent Clock
MICROPROCESSOR IF
Cell Insertion
Cell Extraction
ConÞg Registers
Maintenance Access
UTOPIA IF
MICRO-
PROCESSOR IF
UTOPIA IF
EGRESS PHY IF
CRC Gen (OAM)
MultiPHY Support
EGRESS CELL PROCESSOR
Multicast Translation
Cell Counting
OAM Operations
Address Translation
Microprocessor Cell Insertion/Extraction
EGRESS SWITCH IF
Extract Overhead
CRC Check
Independent Clock
UTOPIA IF
MC92501
2
MOTOROLA


Part Number MC92501
Description ATM Cell Processor
Maker Motorola
Total Page 30 Pages
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