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Motorola Electronic Components Datasheet

MCM62940A Datasheet

32K x 9 Bit BurstRAM Synchronous Static RAM

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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
32K X 9 Bit BurstRAMTM
Synchronous Static RAM
With Burst Counter and Self-Timed Write
MCM62940A
The MCM62940A is a 294,912 bit synchronous static random access memory
designed to provide a burstable, high-performance, secondary cache for the MC68040
and PowerPCTM microprocessors. It is organized as 32,768 words of 9 bits, fabricated
using Motorola's high-performance silicon-gate CMOS technology. The device inte-
grates input registers, a 2-bit counter, high speed SRAM, and high drive capability out-
puts onto a single monolithic circuit for reduced parts count implementation of cache
data RAM applications. Synchronous design allows precise cycle control with the use
of an external clock (K). CMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
Addresses (AO - A14), data inputs (DOO - D08), and all control signals,
except output enable (<3), are clock (K) controlled through positive-edge-trig-
A2
gered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP) or transfer
start cache controller (TSC) input pins. Subsequent burst addresses are gen-
erated internally by the MCM62940A (burst sequence imitates that of the
MC68040) and controlled by the burst address advance (BAA) input pin. The
following pages provide more detailed information on burst controls.
Write cycles are internally self-timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off-chip write pulse generation
and provides increased flexibility for incoming signals.
The MCM62940A is packaged in a 44-pin plastic-leaded chip carrier (PLCC).
A3
A4
A5
A6
VSS
DOO
DOl
VSSO
VCCO
D02
Multiple power and ground pins have been utilized to minimize effects induced
by output noise. Separate power and ground pins have been employed for
DOO - D08 to allow user-controlled output levels of 5 volts or 3.3 volts.
• Single 5 V ± 10% Power Supply
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility
• Fast Access Times: 11/12114/19/24 ns Max, Cycle Times: 15/20/20/25/30 ns Min
• Internal Input Registers (Address, Data, Control)
Internally Self-Timed Write Cycle
• TSP, TSC, and BAA Burst Control Pins
• Asynchronous Output Enable Controlled Three-State Outputs
• Common Data Inputs and Data Outputs
• High Output Drive Capability: 85 pF per I/O
• High Board Density PLCC Package
• Fully TTL-Compatible
• Active High and Low Chip Select Inputs for Easy Depth Expansion
FN PACKAGE
44·lEAO PlCC
CASE 777
PIN ASSIGNMENT
5 4 3 2 1 44 43 42 4140
39
38
37
36
35
34
33
32
31
30
17 29
18 19 20 21 22 23 24 2526 2728
All
A12
A13 _ _ _
A14-..
VSS
D07
D06
VSSO
VCCO
D05
D04
PIN NAMES
AO -A14 ............ Address Inputs
K ........................... Clock
W .............. Synchronous Write
G .................. Output Enable
SO, S1 .......•........ Chip Selects
BAA ..... . .. Burst Address Advance
TSP, TSC ............ Transfer Start
000 - DOS. . . . . .. Data InpuVOutput
VCC ............ + 5 V Power Supply
Vcca ... Output Buffer Power Supply
VSS ....•...•....•........ Ground
Vssa ........ Output Buffer Ground
All power supply and ground pins must
be connected for proper operation of the
device. VCC~VCcaatalitimesincluding
power up.
BurstRAM is a trademark of Motorola, Inc.
PowerPC is a trademark of IBM Corp.
MOTOROLA FAST SRAM DATA
MCM62940A
4-85


Motorola Electronic Components Datasheet

MCM62940A Datasheet

32K x 9 Bit BurstRAM Synchronous Static RAM

No Preview Available !

BLOCK DIAGRAM (See Note)
BAA-----------------------------a
K----------~--------------._--,
BURST LOGIC
BINARY
COUNTER
INTERNAL
Ql
I
Al'
- -_
ADDRESS
_-,-~--~
15
r-~--~------.------iLOAD
01
ao AO'
DO
EXTERNAL
ADDRESS
A14-AO -+---------,~
ADDRESS
REGISTERS
Al AO
Al4-A2
15
32Kx9
MEMORY
ARRAY
I W-----a
WRITE
REGISTER
DATA·IN
REGISTERS
SO------------~
51-------------0
ENABLE
REGISTER
OUTPUT
BUFFER
G----------------------------------~
~oa8~--___,~--------------------------------------------------------~~------~
NOTE: All registers are positive-edge triggered. The TSC orTSP signals control the duration ofthe burst and the start ofthe next burst.When TSP
is sampled low, any ongoing burst is interrupted and a read (independent of Wand TSC) is performed using the new external address.
When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed
using the next extemal address. Chip selects (SO, Sl) are sampled only when a new base address is loaded. After the first cycle of the
burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the operation. When
BAA is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion
of a burst, the address will wrap around to its initial state. See BURST SEQUENCE GRAPH.
BURST SEQUENCE GRAPH (See Note)
rO'O~
~'.OJ'A1', AO'=
NOTE: The external two values for Aland AO .
provide the starting point for the burst
sequence graph. The burst logic ad-
vances Aland AO as shown above.
MCM62940A
4-86
MOTOROLA FAST SRAM DATA


Part Number MCM62940A
Description 32K x 9 Bit BurstRAM Synchronous Static RAM
Maker Motorola
Total Page 8 Pages
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