32K X 9 Bit BurstRAMTM
Synchronous Static RAM
With Burst Counter and Self-Timed Write
The MCM62940A is a 294,912 bit synchronous static random access memory
designed to provide a burstable, high-performance, secondary cache for the MC68040
and PowerPCTM microprocessors. It is organized as 32,768 words of 9 bits, fabricated
using Motorola's high-performance silicon-gate CMOS technology. The device inte-
grates input registers, a 2-bit counter, high speed SRAM, and high drive capability out-
puts onto a single monolithic circuit for reduced parts count implementation of cache
data RAM applications. Synchronous design allows precise cycle control with the use
of an external clock (K). CMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
Addresses (AO - A14), data inputs (DOO - D08), and all control signals,
except output enable (<3), are clock (K) controlled through positive-edge-trig-
gered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP) or transfer
start cache controller (TSC) input pins. Subsequent burst addresses are gen-
erated internally by the MCM62940A (burst sequence imitates that of the
MC68040) and controlled by the burst address advance (BAA) input pin. The
following pages provide more detailed information on burst controls.
Write cycles are internally self-timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off-chip write pulse generation
and provides increased flexibility for incoming signals.
The MCM62940A is packaged in a 44-pin plastic-leaded chip carrier (PLCC).
Multiple power and ground pins have been utilized to minimize effects induced
by output noise. Separate power and ground pins have been employed for
DOO - D08 to allow user-controlled output levels of 5 volts or 3.3 volts.
• Single 5 V ± 10% Power Supply
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility
• Fast Access Times: 11/12114/19/24 ns Max, Cycle Times: 15/20/20/25/30 ns Min
• Internal Input Registers (Address, Data, Control)
Internally Self-Timed Write Cycle
• TSP, TSC, and BAA Burst Control Pins
• Asynchronous Output Enable Controlled Three-State Outputs
• Common Data Inputs and Data Outputs
• High Output Drive Capability: 85 pF per I/O
• High Board Density PLCC Package
• Fully TTL-Compatible
• Active High and Low Chip Select Inputs for Easy Depth Expansion
5 4 3 2 1 44 43 42 4140
18 19 20 21 22 23 24 2526 2728
A13 _ _ _
AO -A14 ............ Address Inputs
K ........................... Clock
W .............. Synchronous Write
G .................. Output Enable
SO, S1 .......•........ Chip Selects
BAA ..... . .. Burst Address Advance
TSP, TSC ............ Transfer Start
000 - DOS. . . . . .. Data InpuVOutput
VCC ............ + 5 V Power Supply
Vcca ... Output Buffer Power Supply
VSS ....•...•....•........ Ground
Vssa ........ Output Buffer Ground
All power supply and ground pins must
be connected for proper operation of the
BurstRAM is a trademark of Motorola, Inc.
PowerPC is a trademark of IBM Corp.
MOTOROLA FAST SRAM DATA