Datasheet4U Logo Datasheet4U.com

MPC2105C - 512KB and 1MB BurstRAM

Description

Pin Locations 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 62 151 64, 65 149 172 59, 60 30, 56, 115, 144, 146 153, 154 98, 104, 110, 118, 126, 132, 138, 148 4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26

Features

  • n’t care. 2. For a write operation following a read operation, CG must be high before the input data required set.
  • up time and held high through the input data hold time.

📥 Download Datasheet

Datasheet preview – MPC2105C

📁 Similar Datasheet

  • MPC22163-130 - 130A high-efficiency step-down power module (MPS)
  • MPC235 - Low-Speed USB Micro-Controller (Megawin)
  • MPC2510 - Low Voltage PLL Clock Driver (Motorola Semiconductor)
  • MPC2565 - (MPC3590 / MPC2565) COMMON MODE CHOKE (Micro Electronics)
  • MPC2F35 - Low-Speed USB Micro-Controller (Megawin)
  • MPC - POWER FILM CAPACITORS (Rubycon)
  • MPC-P09828 - 55-65GHz Single Side Band Mixer (United Monolithic Semiconductors)
  • MPC01 - (MPC Series) Metal Plate Cement Resistor (Futaba Electric)
  • MPC0730LR20C - SMD Inductors (KEMET)
  • MPC0740LR42C - SMD Inductors (KEMET)
Other Datasheets by Motorola

Full PDF Text Transcription

Click to expand full text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2105C/D 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2105C and the MPC2106C are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2105C and MPC2106C utilize synchronous BurstRAMs. The modules are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format. The MPC2105C uses four of the 3 V 64K x 18; the MPC2106C uses eight of the 3 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used.
Published: |