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Motorola Electronic Components Datasheet

MTB10N40E Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB10N40E/D
Designer's Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor-
mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
G
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
®
D
S
MTB10N40E
Motorola Preferred Device
TMOS POWER FET
10 AMPERES
400 VOLTS
RDS(on) = 0.55 OHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
VDSS
VDGR
VGS
ID
ID
IDM
400 Vdc
400 Vdc
± 20 Vdc
10 Amps
6.0
40 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range
PD
TJ, Tstg
125
1.00
2.5
– 55 to 150
Watts
W/°C
Watts
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vpk, IL = 10 Apk, L = 10 mH, RG = 25 )
EAS 520 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.00 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
©MMoottoororolal,aInTc.M19O9S4 Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB10N40E Datasheet

TMOS POWER FET

No Preview Available !

MTB10N40E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
400
398
— Vdc
— mV/°C
Zero Gate Voltage Drain Current
(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current–Forward
(Vgsf = 20 Vdc, VDS = 0)
Gate–Body Leakage Current–Reverse
(Vgsr = 20 Vdc, VDS = 0)
IDSS
µAdc
— — 0.1
— — 1.0
IGSSF — — 100 nAdc
IGSSR — — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
2.0 2.8 4.0 Vdc
— 6.3 — mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 5.0 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 10 Adc)
(ID = 5.0 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDD = 200 Vdc, ID = 10 Adc,
VGS = 10 Vdc,
RG = 10 )
(VDS = 320 Vdc, ID = 10 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 10 Adc, VGS = 0 Vdc)
(IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— 0.4 0.55 Ohm
Vdc
— 5.61 6.6
— — 5.5
4.0 —
— mhos
1570
2200
pF
— 230 325
— 55 110
— 25 50 ns
— 37 75
— 75 150
— 31 65
— 46 63 nC
— 10 —
— 23 —
———
Vdc
— 0.9 2.0
———
Reverse Recovery Time
(See Figure 14)
Reverse Recovery Stored Charge
(IS = 10 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the tab to center of die)
(Measured from the drain lead 0.25from package to center of die)
trr
QRR
LD
— 250 —
— 3000 —
— 3.5 —
— 4.5 —
ns
nC
nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
LS
— 7.5 — nH
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB10N40E
Description TMOS POWER FET
Maker Motorola
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