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Motorola Electronic Components Datasheet

MTB40N10E Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTB40N10E/D
Advance Data Sheet
TMOS E-FET.
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
®
N–Channel
D
G
MTB40N10E
TMOS POWER FET
40 AMPERES
100 VOLTS
RDS(on) = 0.04 OHM
CASE 418B–03, Style 2
D2PAK
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 75 Vdc, VGS = 10 Vdc, PEAK IL = 40 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
TJ, Tstg
EAS
RθJC
RθJA
RθJA
TL
Value
100
100
± 20
± 40
40
29
140
169
1.35
2.5
– 55 to 150
800
0.74
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 1
© MMoototororloa,laIncT.M19O97S Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB40N10E Datasheet

TMOS POWER FET

No Preview Available !

MTB40N10E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk 2.0) (3)
V(BR)DSS
100
112
Vdc
— mV/°C
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
µAdc
— — 10
— — 100
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
(Cpk 2.0) (3)
VGS(th)
Vdc
2.0 2.9 4.0
— 6.7 — mV/°C
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 20 Adc)
(Cpk 2.0) (3)
RDS(on)
Ohms
0.033
0.04
Drain–to–Source On–Voltage (VGS = 10 Vdc)
(ID = 40 Adc)
(ID = 20 Adc, TJ = 125°C)
Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc)
VDS(on)
Vdc
— — 1.9
— — 1.7
gFS 17 21 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
(VDD = 50 Vdc, ID = 40 Adc,
VGS = 10 Vdc,
RG = 9.1 )
(VDS = 80 Vdc, ID = 40 Adc,
VGS = 10 Vdc)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
2305
3230
pF
— 620 1240
— 205 290
— 19 40 ns
— 165 330
— 75 150
— 97 190
— 80 110 nC
— 15 —
— 40 —
— 29 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 40 Adc, VGS = 0 Vdc)
(IS = 40 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
Vdc
— 0.96 1.0
— 0.88 —
Reverse Recovery Time
(See Figure 14)
Reverse Recovery Stored Charge
(IS = 40 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
trr
ta
tb
QRR
— 152 —
ns
— 117 —
— 35 —
— 1.0 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25from package to center of die)
LD nH
— 3.5 —
— 4.5 —
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
LS
— 7.5 —
+ Ť Ť(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk
Max limit – Typ
3 sigma
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB40N10E
Description TMOS POWER FET
Maker Motorola
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