MTB40N10E Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTB40N10E/D Advance Data Sheet TMOS E-FET.™ Power Field Effect Transistor N- Channel Enhancement- Mode Silicon Gate This advanced TMOS E- FET is designed to withstand high energy in the avalanche and mutation modes. The new energy efficient design also offers a drain- to- source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and mutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. - Avalanche Energy Specified - Source- to- Drain Diode Recovery Time parable to a Discrete Fast Recovery Diode - Diode is Characterized for Use in Bridge Circuits - IDSS and VDS(on) Specified at Elevated Temperature TMOS POWER FET 40 AMPERES 100 VOLTS RDS(on) = 0.04 OHM ® N- Channel D CASE 418B- 03, Style 2 D2PAK G S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain- to- Source Voltage Drain- to- Gate Voltage (RGS = 1.0 MΩ) Gate- to- Source Voltage - Continuous Gate- to- Source Voltage - Non- Repetitive (tp ≤ 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100°C Drain Current - Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C (1) Operating and Storage Temperature Range Single Pulse Drain- to- Source Avalanche Energy - Starting TJ = 25°C (VDD = 75 Vdc, VGS = 10 Vdc, PEAK IL = 40 Apk, L = 1.0 m H, RG = 25 Ω) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Ambient (1) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds (1) When surface mounted to an FR4 board using the minimum remended pad size. This document contains information on a new product. Specifications and information herein are subject to change...