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Motorola Electronic Components Datasheet

MTB50N06EL Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB50N06EL/D
Advance Information
TMOS E-FET.
Power Field Effect Transistors
D2PAK for Surface Mount
Logic Level TMOS (L2TMOSāā)
N–Channel Enhancement–Mode Silicon Gate
These TMOS Power FETs are designed for high speed, low loss
power switching applications such as switching regulators, convert-
ers, solenoid and relay drivers. This Logic Level Series part is
specified to operate with level logic gate–to–source voltage of 5 volt
and 4 volt.
Silicon Gate for Fast Switching Speeds
Low RDS(on) — 0.028 max
Replace External Zener Transient Suppressor — Absorbs High
Energy in the Avalanche Mode
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
MTB50N06EL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
50 AMPERES
60 VOLTS
RDS(on) = 0.028 OHM
®
D
CASE 418B–02, Style 2
D2PAK
S
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vpk, IL = 50 Apk, L = 0.32 mH, RG = 25 )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
RθJC
RθJA
RθJA
TL
60
60
±15
50
28
142
125
1.0
2.5
– 55 to 150
400
1.0
62.5
50
260
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET, Designer’s and L2TMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
©MMoottoororolal,aInTc.M19O9S4 Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB50N06EL Datasheet

TMOS POWER FET

No Preview Available !

MTB50N06EL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 V, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
60 — — Vdc
— 64 — mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0)
(VDS = 60 Vdc, VGS = 0, TJ = 125°C)
Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0)
IDSS
IGSS
µAdc
— — 10
— — 100
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
1.0 — 2.0 Vdc
— 4.78 — mV/°C
Static Drain–Source On–Resistance
(VGS = 5.0 Vdc, ID = 25 Adc)
(VGS = 4.0 Vdc, ID = 25 Adc)
Drain–Source On–Voltage (VGS = 5.0 Vdc)
(ID = 50 Adc)
(ID = 25 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 25 Adc)
RDS(on)
VDS(on)
gFS
17
— 0.028 Ohm
— 0.039
Vdc
— 1.68
— 1.40
— — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0,
f = 1.0 MHz)
Ciss
Coss
Crss
3100
4340
pF
1065
1491
— 260 520
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(VDD = 25 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc,
RG = 9.1 )
(VDS = 48 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
— 21 42 ns
— 365 730
— 55 110
— 150 300
— 52 73 nC
— 13 —
— 34 —
— 27 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 50 Adc, VGS = 0)
(IS = 50 Adc, VGS = 0, TJ = °C)
VSD
Vdc
— 1.52 2.5
— 1.1 —
Reverse Recovery Time
(IS = 50 Adc, VGS = 0 ,
dIS/dt = 100 A/µs)
trr
— 200 —
ns
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the tab to center of die)
Ld — 3.5 — nH
Internal Source Inductance
(Measured from the source lead 0.1from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
Ls
— 7.5 — nH
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB50N06EL
Description TMOS POWER FET
Maker Motorola
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