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Motorola Electronic Components Datasheet

MTB9N25E Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTB9N25E/D
Designer's Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS E–FET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a drain–to–source diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
G
®
D
S
MTB9N25E
Motorola Preferred Device
TMOS POWER FET
9.0 AMPERES
250 VOLTS
RDS(on) = 0.45 OHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS 250 Vdc
Drain–to–Gate Voltage (RGS = 1.0 M)
VDGR 250 Vdc
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp 10 µs)
ID 9.0 Adc
ID 5.7
IDM 32 Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
PD 80 Watts
0.64 W/°C
2.5 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 3.0 mH, RG = 25 )
EAS
mJ
122
Thermal Resistance — Junction to Case
— Junction to Ambient
— Junction to Ambient (1)
RθJC
RθJA
RθJA
1.56 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB9N25E Datasheet

TMOS POWER FET

No Preview Available !

MTB9N25E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V(BR)DSS
250
328
Vdc
— mV/°C
IDSS
µAdc
— — 10
— — 100
IGSS
— — 100 nAdc
VGS(th)
2.0 3.0 4.0 Vdc
— 7.0 — mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 4.5 Adc)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 9.0 Adc)
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 4.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDD = 125 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc,
RG = 9.1 )
(VDS = 200 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 9.0 Adc, VGS = 0 Vdc )
(IS = 9.0 Adc, VGS = 0 Vdc , TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— 0.37 0.45 Ohm
Vdc
— 3.5 5.4
— — 4.7
3.0 5.2
— mhos
783 1100
pF
— 144 200
— 32 65
— 10 20
— 36 70
— 27 55
— 26 50
— 26 40
— 4.8 —
— 12.7 —
— 9.2 —
ns
nC
Vdc
— 0.9 1.5
— 0.81 —
Reverse Recovery Time
(See Figure 14)
(IS = 9.0 Adc, VGS = 0 Vdc,
dlS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
trr
ta
tb
QRR
LD
— 191 —
— 126 —
— 65 —
— 1.387 —
— 4.5 —
ns
µC
nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
LS
nH
— 7.5 —
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB9N25E
Description TMOS POWER FET
Maker Motorola
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