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Motorola Electronic Components Datasheet

MTD9N10E Datasheet

TMOS POWER FET

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MOTOROLA
www.DaStaEShMeeICt4OU.NcoDmUCTOR TECHNICAL DATA
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by MTD9N10E/D
Designer's
Data Sheet
TMOS E-FET .
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Replaces MTD6N10
G
®
D
S
MTD9N10E
Motorola Preferred Device
TMOS POWER FET
9.0 AMPERES
100 VOLTS
RDS(on) = 0.25 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS
VDGR
VGS
VGSM
100
100
± 20
± 30
Vdc
Vdc
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 9.0 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size
Maximum Temperature for Soldering Purposes, 1/8from case for 10 seconds
ID
ID
IDM
PD
TJ, Tstg
EAS
RθJC
RθJA
RθJA
TL
9.0
5.0
27
40
0.32
1.75
– 55 to 150
40
3.13
100
71.4
260
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTD9N10E Datasheet

TMOS POWER FET

No Preview Available !

www.DaMtaTSDh9eNet140UE.com
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 4.5 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 9.0 Adc)
(ID = 4.5 Adc, TJ = 125°C)
Forward Transconductance (VDS = 8.0 Vdc, ID = 4.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 50 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc,
RG = 9.1 )
Gate Charge
(See Figure 8)
(VDS = 80 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 9.0 Adc, VGS = 0 Vdc)
(IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 14)
(IS = 9.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
Symbol
V(BR)DSS
IDSS
IGSS
VGS(th)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
trr
ta
tb
QRR
LD
LS
Min
100
2.0
4.0
Typ Max Unit
— — Vdc
103 — mV/°C
µAdc
— 10
— 100
— 100 nAdc
— 4.0 Vdc
6.0 — mV/°C
0.17 0.25 Ohm
Vdc
— 2.43
— 2.40
— — mhos
610 1200 pF
176 400
14 30
8.8 20 ns
28 60
16 30
4.8 10
14 21 nC
5.2 —
3.2 —
6.6 —
Vdc
0.98 1.8
0.9 —
91 — ns
71 —
20 —
0.4 — µC
4.5 — nH
7.5 — nH
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTD9N10E
Description TMOS POWER FET
Maker Motorola
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