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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MTP36N06V/D
Designer's
TMOS V Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E–FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes.