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Motorola Electronic Components Datasheet

SN74LS395 Datasheet

4-BIT SHIFT REGISTER

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4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate
in either a synchronous parallel load or a serial shift-right mode, as
determined by the Select input. An asynchronous active LOW Master Reset
(MR) input overrides the synchronous operations and clears the register. An
active HIGH Output Enable (OE) input controls the 3-state output buffers, but
does not interfere with the other operations. The fourth stage also has a
conventional output for linking purposes in multi-stage serial operations.
Shift Left or Parallel 4-Bit Register
3-State Outputs
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC O0 O1 O2 O3 Q3 CP OE
16 15 14 13 12 11 10 9
1 2 3 4 56
MR DS P0 P1 P2 P3
78
S GND
PIN NAMES
P0 – P3
DS
S
CP
MR
OE
O0 – O3
Q3
Parallel Inputs
Serial Data Input
Mode Select Input
Clock (Active LOW) Input
Master Reset (Active LOW) Input
Output Enable (Active HIGH) Input
3-State Register Outputs
Register Output
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
5 U.L.
SN74LS395
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN74LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
734 5 6
S P0 P1 P2 P3
2 DS
10 CP
Q3 11
9 OE
MR O0 O1 O2 O3
1 15 14 13 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-551


Motorola Electronic Components Datasheet

SN74LS395 Datasheet

4-BIT SHIFT REGISTER

No Preview Available !

LOGIC DIAGRAM
S
Ds
SN 74LS395
P0 P1
P2
P3
CP
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
MR
OE
FUNCTION DESCRIPTION
O0
O1
The SN74LS395 contains four D-type edge-triggered
flip-flops and auxiliary gating to select a D input either from a
Parallel (Pn) input or from the preceding stage. When the
Select input is HIGH, the Pn inputs are enabled. A LOW signal
on the S input enables the serial inputs for shift-right opera-
tions, as indicated in the Truth Table.
State changes are initiated by HIGH-to-LOW transitions on
the Clock Pulse (CP) input. Signals on the Pn, Ds and S inputs
can change when the Clock is in either state, provided that the
recommended set-up and hold times are observed. When the
O2 O3 Q3
S input is LOW, a CP HIGH-LOW transition transfers data in
Q0 to Q1, Q1 to Q2, and Q2 to Q3. A left-shift is accomplished
by connecting the outputs back to the Pn inputs, but offset one
place to the left, i.e., O3 to P2, O2 to P1 and O1 to P0, with P3
acting as the linking input from another package.
When the OE input is HIGH, the output buffers are disabled
and the Q0 – Q3 outputs are in a high impedance condition.
The shifting, parallel loading or resetting operations can still be
accomplished, however.
MODE SELECT — TRUTH TABLE
Operating Mode
Asynchronous Reset
Shift, SET First Stage
Inputs @ tn
Outputs @ tn+1
MR CP
S Ds Pn O0 O1
O2
L X XX X L L L
H L H X H O0n O1n
Shift, RESET First Stage
Parallel Load
H
H
L L X L O0n O1n
H X Pn P0 P1 P2
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
tn, n + 1 = time before and after CP HIGH-to-LOW transition
NOTE:
When OE is HIGH, outputs O0 – O3 are in the high impedance state; however, this does not affect other operations or the Q3 output.
O3
L
O2n
O2n
P3
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Min Typ Max Unit
4.75 5.0 5.25
V
0 25 70 °C
– 0.4
mA
8.0 mA
FAST AND LS TTL DATA
5-552


Part Number SN74LS395
Description 4-BIT SHIFT REGISTER
Maker Motorola
Total Page 6 Pages
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