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MC68EC040V Datasheet Microprocessor

Manufacturer: Motorola Semiconductor

Overview: w w S a t APPENDIX B a MC68EC040 .D w e e h U 4 t m o .c REV2.2 (11/02/99) NOTE Rev. 2.2 contains timing information for 40 MHz operation. Refer to chang bars. Some TBD values will be filled in shortly. All references to MC68EC040 also apply to the MC68EC040V. Refer to Appendix C MC68040V and MC68EC040V for more information on the MC68EC040V. The MC68EC040 is Motorola's third generation of M68000-compatible, high-performance, 32-bit microprocessors. The MC68EC040 is an embedded controller employing a highly integrated architecture to provide very high performance in a monolithic HCMOS device. The MC68EC040 integrates an MC68040-compatible integer unit, an access control unit (ACU), and independent 4-Kbyte instruction and data caches. A six-stage instruction pipeline, multiple internal buses, and a full internal Harvard architecture, including separate caches for both instruction and data accesses, provides a high degree of instruction execution parallelism. The inclusion of on-chip bus snooping logic, which directly supports cache coherency in multimaster applications, enhances cache functionality. The MC68EC040 is user-object-code compatible with previous members of the M68000 family and is specifically optimized to reduce the execution time of compiler-generated code. The MC68EC040 is pin compatible with the MC68040 and MC68LC040. The MC68EC040 is implemented in Motorola's latest HCMOS technology, providing an ideal balance between speed, power, and physical device size. Figure B-1 provides a simplified block diagram of the MC68EC040.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • of the MC68EC040 include:.
  • MC68040-Compatible Integer Execution Unit.
  • 4-Kbyte Instruction Cache and 4-Kbyte Data Cache Accessible Simultaneously.
  • 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Bursting Interface.
  • User-Object-Code Compatible with All M68000 Microprocessors.
  • Concurrent Integer Unit, ACU, and Bus Controller Operation Maximizes Throughput.
  • Low-Latency Bus Accesses for Reduced Cache-Miss Penalty.

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