MC9S08DE32
Description
of Changes Advance Information version for alpha samples customers Product Launch. Removed the 64-pin QFN package.
Key Features
- 40-MHz HCS08 CPU (20-MHz bus)
- HC08 instruction set with added BGND instruction
- Support for up to 32 interrupt/reset sources Peripherals
- ADC - 24-channel, 12-bit resolution, 2.5 μs conversion time, automatic compare function, temperature sensor, internal bandgap reference channel
- ACMPx - Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage
- MSCAN - CAN protocol - Version 2.0 A, B; standard and extended data frames; support for remote frames; five receive buffers with FIFO storage scheme; flexible identifier acceptance filters programmable as: 2 x 32-bit, 4 x 16-bit, or 8 x 8-bit
- SCIx - Two SCIs supporting LIN 2.0 Protocol and SAE J2602 protocols; full duplex non-return to zero (NRZ); master extended break generation; slave extended break detection; wakeup on active edge
- SPI - Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting
- IIC - Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; general call address; Interrupt driven byte-by-byte data transfer
- TPMx - One 6-channel (TPM1) and one 2-channel (TPM2); selectable input capture, output compare, or buffered edge-aligned PWM on each channel
