MU9C Binary Routing Coprocessor (RCP) Family
The MU9C RCP family consists of 4K and 8K x 64-bit
Routing Coprocessors (RCPs) with a 32-bit wide data
interface. The device is designed for use in layer 2
switches to provide very high throughput address
translation using tables held in external RAM. The MU9C
RCP has a fully deterministic search time, independent of
the size of the list and the position of the data in the list.
This unique feature guarantees that the wire speed address
recognition does not impact the latency or induce some
jitter on the latency of the global system. Address fields
from the packet header are compared against a list of
entries stored in the array. As a result of the comparison,
the MU9C RCP generates an index that is used to access
an external RAM where port mapping data and other
associated information is stored.
A set of control states provides a powerful and flexible
control interface to the MU9C RCP. This control structure
allows memory read and write, register read and write,
data move, comparison, validity control, addressing
control, and initialization operations.
The MU9C RCP architecture uses direct hardware control
of the device and an independent bus for returning match
results. Software control is also supported for systems
where maximum performance is not needed.
The MU9C RCP is designed to act as an address translator
for lookup tables in layer 2 switches. Refer to Figure 2 for
a simplified block diagram of a switch. During normal
operation, the controller extracts the address information
from an arriving packet to form the comparand, which is
then compared against the contents of the MU9C RCP.
The MU9C RCP generates an index that is used to access
the data in an external RAM, which holds the destination
port for accessing the network. The controller reads the
data from the RAM and forwards the packet.
The validity of a location in the Address Database is
determined by an extra bit called the Validity bit. This bit is
set and reset either with an index or an associative match.
Therefore, when a new entry is written to the database, its
Validity bit is set valid. The index at which a write takes
place is driven onto the PA:AA bus, so that output port
data can be written simultaneously into the external RAM
at the correct index.
When a database location is deleted, the Validity bit for that
entry is reset, and the index of the location is driven onto
the Active Address bus. This simple mechanism allows
easy maintenance of the tables in both the database and the
The MU9C RCP supports simple daisy chained vertical
cascading that serves to prioritize multiple devices and
provides system-level match and full indication. If the
slight timing overhead associated with the daisy chain is
unacceptable, the MU9C RCP is designed to facilitate
external prioritization across multiple devices.
and Packet Data
Figure 2: Switch Block Diagram
2 Rev. 6