PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
16 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE
The MC-45D16CA721 is a 16,777,216 words by 72 bits DDR synchronous dynamic RAM module on which 9 pieces
of 128M DDR SDRAM: µPD45D128842 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
• 16,777,216 words by 72 bits organization (ECC type)
• Clock frequency
CL = 2.5
CL = 2
CL = 2.5
CL = 2
• Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• 2.5 V ± 0.2 V Power supply for VDD
• 2.5 V ± 0.2 V Power supply for VDDQ
• SSTL_2 compatible with all signals
• 4,096 refresh cycles / 64 ms
• Burst termination by Precharge command and Burst stop command
• 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14898EJ2V0DS00 (2nd edition)
Date Published June 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.