MC-45D32CD641 Datasheet | NEC

PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT 32 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE Description The MC-45D32CD641 is a 33,554,432 words by 64 bits DDR synchronous dynamic RAM module on which 16 pieces of 128M DDR SDRAM: µPD45D128842 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features - 33,554,432 words by 64 bits organization - Clock frequency Part number /CAS latency Clock frequency (MAX.) MC-45D32CD641KFA-C75 CL = 2.5 CL = 2 MC-45D32CD641KFA-C80 CL = 2.5 CL = 2 133 MHz 100 MHz 125 MHz 100 MHz DDR SDRAM Unbuffered DIMM Design specification Rev.0.9 pliant Module type - Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge - Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK - Quad internal banks operation - Possible to assert random column address in every clock cycle - Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) - Automatic precharge and controlled precharge - CBR (Auto) refresh and self refresh - 2.5 V ± 0.2 V Power supply for VDD - 2.5 V ± 0.2 V Power supply for VDDQ - SSTL_2 patible with all signals - 4,096 refresh cycles / 64 ms - Burst termination by Precharge mand and Burst stop mand - 184-pin dual in-line memory module (Pin pitch = 1.27 mm) - Unbuffered type - Serial PD The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and...