UPD16675A Datasheet | NEC

FEATURES - LCD driver with built-in display RAM - Can operate on a single 3-V power supply - Booster circuit incorporated: Switchable between 2X & 3X - Dot display RAM: 128 × 32 bits - Pictographic display RAM (portion of two lines): 128 × 2 bits - Pictographic display RAM duty changeable: 1/34 and 2/36 duties - Output: 128 segments & 34 mons - Data input based on serial & 4-/8-bit parallel switchover - Split resistor incorporated - Oscillation circuit incorporated ORDERING INFORMATION Part Number Package Chips/wafer (Matched COG mounting) 2-side standard TCP (Output OLB: 0.25 mm pitch) TCP (TAB) µPD16675AP/W µPD16675AN-051 µPD16675AN-xxx Purchasing the above products in terms of chips per wafer requires an exchange of other documents as well, including a memorandum on the product quality. Therefore, those who are interested in this regard are advised to contact an NEC sales representative for further details. The information in this document is subject to change without notice. Document No. S11195EJ1V0DS00 (1st edition) Date Published July 1998 NS CP (K) Printed in Japan © 1 DACHA VCHA VEXT VLC5 VLC4 VLC3 VLC2 VLC1 Amp IN( ) Amp IN( ) VLCD C1 C1 C2 C2 OSCBRI POCOUT SYNC CLKOUT D7 / NS D6 / CAE D5 D4 D3 D2 D1 D0 / DATA WS CS0 CS1 CS2 OSCIN OSCOUT DC / DC Converter 32 P1,P2 SEG1 SEG128 mon Driver 34 34 Bits Register LCD Voltage Controller Segment Driver 128 128 Bits Latch 128 Pict Data Memory (128 Blink Data Memory (128 Data Memory Bank 0 (128 Data Memory Bank 1 (128 Data Memory Bank 2 (128 Data Memory Bank 3 (128 Blink Controller Pict Data Memory (128 Blink Data Memory (128 8 Display Mode Reg. Mode Reg. 1 Bits) 1 Bits) 8 Bits) 8 Bits) 8 Bits) 8 Bits) 8 8 8 8 8 8 8 8 8 Read/Write Buffer 8 LCD Timing Controller 1 Bits) 1 Bits) BLOCK DIAGRAM CPU Interface Clock Buffer Address Controller Memory Data Pointer A0-A7 8 mand Decoder Clock 8 STB E / SCK Read / Write Controller mand / Data Controller µPD16675A µPD16675A PIN CONFIGURATION (PAD...