UPD70208H Datasheet | NEC

DESCRIPTION The µ PD70208H (V40HL) is a high-speed, low-power 16-/8-bit microprocessor based on the µ PD70208 (V40TM) with 16-bit architecture, 8-bit data bus, and general-purpose peripheral functions. The µ PD70216H (V50HL) is a high-speed, low-power 16-bit microprocessor based on the µ PD70216 (V50TM ) with 16bit architecture, 16-bit data bus, and general-purpose peripheral functions. The V40HL and V50HL offer 20 MHz operation, and in addition to the conventional standby functions, also allows the clock to be stopped by the use of fully static internal circuitry, thus achieving greatly reduced power consumption. It is also capable of 3 V operation in addition to the previous 5 V operation, making it ideally suited to battery driven systems. Details are given in the following manuals. Be sure to read when carrying out design work. - V40HL, V50HL User’s Manual - Hardware (U11610E) - 16-bit V series TM User’s Manual - Instruction (U11301J: Japanese version) FEATURES - - High-speed, low-power version of V40 and V50 High-performance CPU (V20TM /V30TM software patible) - Minimum instruction execution time: - Memory addressing space: 1M bytes - High-speed multiply/divide instructions: 100 ns (20 MHz, 5 V) 200 ns (10 MHz, 3 V) 0.95 to 2.8 µs (20 MHz, 5 V) 1.9 to 5.6 µs (10 MHz, 3 V) - Maskable (ICU) & non-maskable (NMI) interrupt inputs - µPD8080AF emulation function - Standby functions, clock stoppage capability Standard peripheral LSI functions on chip - - - - - - - Clock generator (CG) Programmable wait control unit (WCU) Refresh control unit (REFU) Timer/counter unit (TCU) - - - µ PD71054 subset Serial control unit (SCU) - - - µ PD71051 subset Interrupt control unit (ICU) - - - µ PD71059 subset DMA control unit (DMAU) - - - µ PD71071/71037 subset (functions of either selectable) 10/12.5/16/20 MHz (at 5 V, with 20/25/32/40 MHz supplied externally) 5/6.25/8/10 MHz (at 3 V, with 10/12.5/16/20 MHz supplied externally) - - Operating frequency: The information in this...