PA102FDG - P-Channel Logic Level Enhancement

This page provides the datasheet information for the PA102FDG, a member of the PA102FDG-NIKO P-Channel Logic Level Enhancement family.

NIKO-SEM

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Datasheet Details

Part number	PA102FDG
Manufacturer	NIKO-SEM
File Size	261.06 KB
Description	P-Channel Logic Level Enhancement
Datasheet	PA102FDG Datasheet
Additional preview pages of the PA102FDG datasheet.

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Full PDF Text Transcription

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NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor PA102FDG TO-252 Lead-Free PRODUCT SUMMARY V(BR)DSS RDS(ON) -20 115m ID -10A D G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current1 TC = 25 °C TC = 70 °C Power Dissipation TC = 25 °C TC = 70 °C Operating Junction & Storage Temperature Range VDS VGS ID IDM PD Tj, Tstg THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL Junction-to-Case RθJC Junction-to-Ambient RθJA 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1% 1 :GATE 2 :DRAIN 3 :SOURCE LIMITS -20 ±12 -10 -6.2 -24 25 9.

Published: Jan 24, 2015 |