74ABT16899 Datasheet | NXP Semiconductors

FEATURES - Symmetrical (A and B bus functions are identical) - Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT/H16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. - Independent transparent latches for A-to-B and B-to-A directions - Selectable ODD/EVEN parity - Continuously checks parity of both A bus and B bus latches as ERRA and ERRB FUNCTIONAL DESCRIPTION The 74ABT/H16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) municates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) municates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of: - Open-collector ERR output - Ability to simultaneously generate and check parity - Can simultaneously read/latch A and B bus data - Output capability: +64 m A/- 32m A - Latch-up protection exceeds 500m A per Jedec Std 17 - ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model - Power up 3-State - Power-up reset - Live insertion/extraction permitted - Bus-hold data inputs eliminate the need for external...